Field of the Disclosure
The present disclosure generally relates to processors and, more particularly, to scheduling instructions based on source availability.
Description of the Related Art
Processors enhance processing efficiency by employing out-of-order execution, whereby instructions are executed in an order different from the program order of the instructions. A scheduler in the processor schedules and tracks instructions to identify when instructions are eligible for execution. A given instruction may have a plurality of sources for data on which it operates. For example, the given instruction may require data retrieved by a previous load operation or data from a previous arithmetic instruction. Thus, a source identifier may reference a load/store unit for data retrieved from the memory hierarchy, a physical register file in the processor, or an output of an execution unit. Such an instruction is referred to as a dependent instruction of the previous load instruction and/or the previous arithmetic instruction. The scheduler has a plurality of entries for holding instructions and each entry has a plurality of source slots that identify the sources for the instruction. The scheduler tracks source ready bits for each of the entries across all of the source slots, so that when all of the sources for an instruction are available, the instruction can be made eligible for execution.
When a given instruction is scheduled for execution, its resultant data is considered available as a source for its dependent instructions during a subsequent execution cycle. If the newly available source results in a particular dependent instruction having all of its sources available, the dependent instruction is eligible to be picked for execution in the next cycle. The scheduler broadcasts a destination identifier, referred to herein as a “source tag,” identifying the source associated with the picked instruction to allow the source tracking information for the other instruction entries to be updated. This arrangement of source status tracking and broadcasting source tags to update the tracking information creates a loop-based timing path. The timing for such a path is difficult to implement as the logic must broadcast source tags across all entries and all of the source slot tracking bits to identify ready instructions for the next cycle. Increasing the size of the scheduler queue to enhance the out-of-order capabilities of the processor creates exacerbates the timing problem.
The use of the same reference symbols in different drawings indicates similar or identical items.